To improve the performance of a processor, there is a bypass function that uses output data from an arithmetic unit as succeeding input data before the results of a preceding instruction are output from the arithmetic unit and written to a floating-point register when an arithmetic operation is performed by obtaining the input data of the arithmetic operation. Circuitry for detecting a dependency on the output of the preceding instruction is required to implement this bypass function.
In the meantime, a register address of a floating-point register, for example, in a SPARC-V9 (SPARC: registered trademark) architecture is 5 bits. Therefore, 32 instructions can be made. FIG. 1 shows a configuration of floating-point registers in the SPARC-V9 architecture. 32 single-precision floating-point registers (4 bytes) are represented as % f0, % f1, % f2, . . . , % f30, % f31, and 32 double-precision floating-point registers (8 bytes) are represented as % d0, % d2, % d4, . . . , % d62. For a double-precision floating-point register, its address can be specified only with an even number. The assignment of a double-precision floating-point register % d(n) (0≦n≦30) (8 bytes) corresponds to the merging of two single-precision floating-point registers % f(n) (4 bytes) and % f(n+1) (4 bytes).
Assume that a single-precision floating-point register is used as a 4-byte register and a double-precision floating-point register is used as an 8-byte register, into which two single-precision floating-point registers are merged, as in the SPARC-V9 architecture. For example, if an arithmetic operation for inputting double-precision floating-point data (8 bytes) to the register % d0 is performed, two output timings of the registers % f0 (4 bytes) and % f1 (4 bytes) must be detected to implement the above described bypass function. As a result, dependency detecting circuitry for the double-precision floating-point registers % d0 to % d30 requires a lot more circuitry amount than that required to only detect dependencies among 8-byte registers.
If the amount of circuitry increases in a processor, not only its cost performance but also its operating frequency drops. This leads to degradation in the performance of the processor. Accordingly, it is required to reduce the amount of circuitry in the processor as much as possible.